Technical Field
This disclosure relates to integrated circuit devices, and more specifically, to a structure and method for fabricating the structure where damage to a metallization layer is repaired.
Background of the Related Art
Semiconductor devices include a plurality of circuits that form an integrated circuit (IC) fabricated on a semiconductor substrate. A complex network of conductive wiring connects the circuit elements distributed on the surface of the substrate. Efficient routing of the wiring for the device requires formation of multilevel or multilayered schemes, such as, for example, single or dual damascene wiring structures. The wiring typically includes copper, Cu, or a Cu alloy since Cu-based interconnects provide higher speed signal transmission as compared with aluminum-based interconnects. Other metals such as tungsten, W, are used for specialized purposes as an interconnect. Within a typical interconnect structure, metal vias run perpendicular to the semiconductor substrate and metal lines run parallel to the semiconductor substrate.
The interconnect structure must connect electrically to the device regions defined in the semiconductor substrate. This substrate usually involves a passivating and an insulating layer required to form and isolate different device regions. Openings through these layers are filled by conductive vias to allow electrical contact to be made selectively to the underlying device regions.
In its simplest form, the opening through which a via is formed is created by first masking the insulating layer, e.g., a dielectric layer, with photoresist and then selectively etching a portion of the insulating layer. The opening formed in the photoresist using well known photolithographic techniques is etched to form an opening to the underlying device or conductive layer. Depending on the aspect ratio and the interconnection ground rules, isotropic or anisotropic etching processes may be used to form a hole in the insulating layer. Subsequent layers of lines above the via are also defined by means of a lithography and etch process. Good contact between the metal lines and vias is necessary to allow proper functioning and reliability of the integrated circuit
The embodiments discussed below relate to improved structures for providing good contact between a conductive via and an overlying conductive metal lines, as well as to methods for making such structures in semiconductor devices.